1. Field of the Invention
The present invention relates to the technical field of processing a signal according to a time division multiplex mode, and more particularly, to an apparatus and method for compensating for the difference between the phase of each signal at the point of generation and the phase of each signal after time division multiplexing.
2. Description of the Related Art
In a time division multiplex mode, as widely known, a plurality of input signals are sequentially arranged in the time domain without being superposed when they are transmitted. Such a time division multiplex mode is applied to a variety of electronic equipment to reduce complexity in hardware and to reduce the price of the system.
For example, when it is necessary to convert a plurality of digital signals into analog signals, hardware can be configured such that separate digital-to-analog (D/A) converters can be provided for the individual digital signals. However, in this case, the hardware becomes complex, and the price of the system increases.
When a time division multiplexing unit is provided prior to a D/A converter, a plurality of digital signals can be converted into analog signals using only one D/A converter. In other words, the time division multiplexing unit allocates the plurality of digital signals based on the time domain and sequentially supplies the allocated signals to the D/A converter so that analog signals corresponding to the plurality of digital signals can be obtained using only one D/A converter.
FIG. 1 shows an example of an apparatus including a time division multiplexing unit and a single D/A converter, as described above. FIG. 2 shows an example of data flow for explaining the operations of the apparatus of FIG. 1. Signal processing according to conventional time division multiplexing will now be described with reference to FIGS. 1 and 2.
When digital signals A (A0, A1, A2, A3, . . . ), B (B0, B1, B2, B3, . . . ) and C (C0, C1, C2, C3, . . . ) are transmitted from first through third digital signal generation logic units 101, 102 and 103 in a digital signal generation logic unit group 100 to a multiplexing unit 110, the multiplexing unit 110 allocates the input signals based on a time domain according to a control signal from a controller 120 in the form of A0, B0, C0, A1, B1, C1, . . . , as shown in FIG. 2. Subsequently, the multiplexing unit 110 outputs the signals. The control signal contains arrangement information indicating the order in which the signals inputted to the multiplexing unit 110 are selected, and information indicating the delay time for each input signal.
For example, in the case of selecting and transmitting the digital signals A, B and C, input to the multiplexing unit 110 in that order, the arrangement information designates a selection order so that the digital signal A can be selected in the first place, the digital signal B can be selected in the second place, and the digital signal C can be selected in the third place. When the next digital signal is transmitted the delay time is the standby duration of the next digital signal. Accordingly, when the digital signals A, B and C are transmitted in that order, a delay time applied to the digital signal B is different from the delay time applied to the digital signal C. In other words, the delay time for the digital signal C is longer than the delay time for the digital signal B. When the delay time is determined, the operation conditions of the multiplexing unit 110, the D/A converter 130 and the first through third sampling and holding units 141–143 are considered.
The D/A converter 130 converts the digital signal which has been multiplexed and transmitted, as shown in FIG. 2, into an analog signal and transmits the analog signal to the first through third sampling and holding units 141–143 at the same time. Each of the first through third sampling & holding units 141–143 samples and holds certain portions of the input signal, as shown in FIG. 2, in response to a corresponding “sample-hold” signal which is generated by the multiplexing unit 110 during the time division multiplexing. In other words, the first sampling and holding unit 141 samples and holds the signals A0, A1, A2, A3, . . . converted into an analog signal. The second sampling and holding unit 142 samples and holds the signals B0, B1, B2, B3, . . . converted into an analog signal. The third sampling and holding unit 143 samples and holds the signals C0, C1, C2, C3, . . . converted into an analog signal.
The signals sampled and held by the first through third sampling and holding units 141–143 are transmitted to first through third low-pass filters (LPFs) 151–153, respectively. Each of the first through third LPFs 151–153 removes a high frequency component from the input signal. Delay times, which have been applied for time division multiplexing performed by the multiplexing unit 110, are maintained in outputs 2 and 3 from the second and third LPFs 152 and 153, as shown in FIG. 2.
As described above, due to phase delays according to time division multiplexing, the phase relation among digital signals at the point of generation is different to that among the digital signals after time division multiplexing. Accordingly, an error occurs as a result of using the outputs 1, 2 and 3 from the first through third LPFs 151–153.
For example, in the case of a projection television, a total of 6 control signals are horizontally and vertically used for R, G and B signals to control convergence. When these control signals are provided according to time division multiplexing, as shown in FIG. 1, delay effects according to the time division multiplexing exist in the control signals. Accordingly, the phase relation among the R, G and B signals at the point of generation is different from that among the R, G and B signals after the time division multiplex, and a horizontal phase is different to a vertical phase, thereby disturbing convergence.